View W3EG72128SXXXD4ISG_3307009.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary* operating frequencies ddr333 @cl=2.5 ddr266 @cl=2 ddr266 @cl=2.5 ddr200 @cl=2 clock speed 166mhz 133mhz 133mhz 100mhz cl-t rcd -t rp 2.5-3-3 2-2-2 2.5-3-3 2-2-2 1gb C 2x64mx72 ddr sdram unbuffered ecc w/pll features double-data-rate architecture ddr200, ddr266 and ddr333 bi-directional data strobes (dqs) differential clock inputs (ck & ck#) programmable read latency 2,2.5 (clock) programmable burst length (2,4,8) programmable burst type (sequential & interleave) edge aligned data output, center aligned data input auto and self refresh serial presence detect dual rank power supply: 2.5v 0.20v jedec standard 200 pin so-dimm package ? package height options: ad4: 35.5 mm (1.38") and bd4: 31.75 mm (1.25") note: consult factory for availability of: ? rohs compliant products ? vendor source control options ? industrial temperature option description the w3eg72128s is a 2x64mx72 double data rate sdram memory module based on 512mb ddr sdram components. this module consists of eighteen 64mx8 bit ddr sdrams in 66 pin tsop packages mounted on a 200 pin fr4 substrate. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system ap pli ca tions. * this product is under development, is not quali? ed or characterized and is subject to change without notice.
2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary pin# symbol pin# symbol pin# symbol pin# symbol 1v ref 51 v ss 101 a9 151 dq42 2v ref 52 v ss 102 a8 152 dq46 3v ss 53 dq19 103 v ss 153 dq43 4v ss 54 dq23 104 v ss 154 dq47 5 dq0 55 dq24 105 a7 155 v cc 6 dq4 56 dq28 106 a6 156 v cc 7 dq1 57 v cc 107a5157v cc 8 dq5 58 v cc 108 a4 158 nc 9v cc 59 dq25 109 a3 159 v ss 10 v cc 60 dq29 110 a2 160 nc 11 dqs0 61 dqs3 111 a1 161 v ss 12 dqm0 62 dqm3 112 a0 162 v ss 13 dq2 63 v ss 113 v cc 163 dq48 14 dq6 64 v ss 114 v cc 164 dq52 15 v ss 65 dq26 115 a10/ap 165 dq49 16 v ss 66 dq30 116 ba1 166 dq53 17 dq3 67 dq27 117 ba0 167 v cc 18 dq7 68 dq31 118 ras# 168 v cc 19 dq8 69 v cc 119 we# 169 dqs6 20 dq12 70 v cc 120 cas# 170 dqm6 21 v cc 71 cb0 121 cs0# 171 dq50 22 v cc 72 cb4 122 cs1# 172 dq54 23 dq9 73 cb1 123 nc 173 v ss 24 dq13 74 cb5 124 nc 174 v ss 25 dqs1 75 v ss 125 v ss 175 dq51 26 dqm1 76 v ss 126 v ss 176 dq55 27 v ss 77 dqs8 127 dq32 177 dq56 28 v ss 78 dqm8 128 dq36 178 dq60 29 dq10 79 nc 129 dq33 179 v cc 30 dq14 80 cb6 130 dq37 180 v cc 31 dq11 81 v cc 131 v cc 181 dq57 32 dq15 82 v cc 132 v cc 182 dq61 33 v cc 83 cb3 133 dqs4 183 dqs7 34 v cc 84 cb7 134 dqm4 184 dqm7 35 ck0 85 nc 135 dq34 185 v ss 36 v cc 86 nc 136 dq38 186 v ss 37 ck0# 87 v ss 137 v ss 187 dq58 38 v ss 88 v ss 138 v ss 188 dq62 39 v ss 89 nc 139 dq35 189 dq59 40 v ss 90 v ss 140 dq39 190 dq63 41 dq16 91 nc 141 dq40 191 v cc 42 dq20 92 v cc 142 dq44 192 v cc 43 dq17 93 v cc 143 v cc 193 sda 44 dq21 94 v cc 144 v cc 194 sa0 45 v cc 95 cke1 145 dq41 195 scl 46 v cc 96 cke0 146 dq45 196 sa1 47 dqs2 97 nc 147 dqs5 197 v ccspd 48 dqm2 98 nc 148 dqm5 198 sa2 49 dq18 99 a12 149 v ss 199 v ccid 50 dq22 100 a11 150 v ss 200 nc pin configuration a0-a12 address input (multiplexed) ba0-ba1 bank select address dq0-dq63 data input/output dqs0-dqs8 data strobe input/output ck0 clock input ck0# clock input cke0, cke1 clock enable input cs0#, cs1# chip select input ras# row address strobe cas# column address strobe we# write enable dqm0-dqm8 data-in mask v cc power supply (2.5v) v ss ground v ref power supply for reference v ccspd serial eeprom power supply (2.3v to 3.6v) sda serial data i/o scl serial clock sa0-sa2 address in eeprom v ccid v cc indenti? cation flag nc no connect pin names
3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary functional block diagram dqs2 dqm2 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs cs# dqs3 dqm3 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs cs# dqs8 dqm8 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs cs# cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs cs# dqs1 dqm1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs cs# dqs5 dqm5 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs cs# dqs6 dqm6 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs cs# dqs7 dqm7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs cs# dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm cs# dqs cs# cs1# cs0# dqs0 dqm0 dqs4 dqm4 ras# r a s # cas# c a s # ba0-ba1 b a 0 - b a 1 we# w e # a0-a12 a 0 - a 1 2 cke0 c k e 0 cke1 c k e 1 ras: ddr sdrams r a s : d d r s d r a m s cas: ddr sdrams c a s : d d r s d r a m s ba0-ba1: ddr sdrams b a 0 - b a 1 : d d r s d r a m s we: ddr sdrams w e : d d r s d r a m s a0-a12: ddr sdrams a 0 - a 1 2 : d d r s d r a m s cke0: ddr sdrams c k e 0 : d d r s d r a m s cke1: ddr sdrams c k e 1 : d d r s d r a m s serial pd scl sda a0 a1 a2 sa0 sa1 sa2 ddr sdram d d r s d r a m ddr sdram d d r s d r a m v cc c c gnd g n d 120? pll p l l v cc ck0 clk0/clk0# clk1/clk1# clk2/clk2# clk3/clk3# ck0# ck0a ck0a# feedback note: all datalines are terminated through a 22 ohms series resistor.
4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary absolute maximum ratings parameter symbol value units voltage on any pin relative to v ss v in , v out -0.5 to 3.6 v voltage on v cc supply relative to v ss v cc , v ccq -1.0 to 3.6 v storage temperature t stg -55 to +150 c power dissipation p d 9w short circuit current i os 50 ma note: permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. dc characteristics 0c t a 70c, v cc = 2.5v 0.2v capacitance t a = 25c, f = 1mhz, v cc = 3.3v, v ref =1.4v 200mv parameter symbol min max unit supply voltage v cc 2.3 2.7 v supply voltage v ccq 2.3 2.7 v reference voltage v ref v ccq/2 - 50mv v ccq/2 + 50mv v termination voltage v tt v ref - 0.04 v ref + 0.04 v input high voltage v ih v ref + 0.15 v ccq + 0.3 v input low voltage v il -0.3 v ref - 0.15 v output high voltage v oh v tt + 0.76 v output low voltage v ol v tt - 0.76 v parameter symbol max unit input capacitance (a0-a12) c in1 56 pf input capacitance (ras#, cas#, we#) c in2 56 pf input capacitance (cke0) c in3 29 pf input capacitance (ck0,ck0#) c in4 5.5 pf input capacitance (cs0#) c in5 29 pf input capacitance (dqm0-dqm8) c in6 13 pf input capacitance (ba0-ba1) c in7 56 pf data input/output capacitance (dq0-dq63)(dqs) c out 13 pf
5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary idd specifications and test conditions recommended operating conditions, 0c t a 70c, v ccq = 2.5v 0.2v, v cc = 2.5v 0.2v parameter symbol conditions ddr333@cl=2.5 max ddr266@cl=2 max ddr266@cl=2.5 max ddr200@cl=2 max units operating current i dd0 one device bank; active - precharge; t rc =t rc (min); t ck =t ck (min); dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two cycles. 2620 2620 2620 2620 ma operating current i dd1 one device bank; active-read- precharge; burst = 2; t rc =t rc (min) ;t ck =t ck (min); iout = 0ma; address and control inputs changing once per clock cycle. 2890 2890 2890 2890 ma precharge power- down standby current i dd2p all device banks idle; power- down mode; t ck =t ck (min); cke=(low) 90 90 90 90 ma idle standby current i dd2f cs# = high; all device banks idle; t ck =t ck (min); cke = high; address and other control inputs changing once per clock cycle. vin = vref for dq, dqs and dm. 1085 1085 1085 1085 ma active power-down standby current i dd3p one device bank active; power-down mode; t ck (min); cke=(low) 630 630 630 630 ma active standby current i dd3n cs# = high; cke = high; one device bank; active-precharge; t rc =t ras (max); t ck =t ck (min); dq, dm and dqs inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle. 1175 1175 1175 1175 ma operating current i dd4r burst = 2; reads; continous burst; one device bank active;address and control inputs changing once per clock cycle; t ck =t ck (min); iout = 0ma. 2935 2935 2935 2935 ma operating current i dd4w burst = 2; writes; continous burst; one device bank active; address and control inputs changing once per clock cycle; t ck =t ck (min); dq,dm and dqs inputs changing twice per clock cycle. 3025 2845 2845 2845 ma auto refresh current i dd5 t rc =t rc (min) 4060 4060 4060 4060 ma self refresh current i dd6 cke 0.2v 360 365 365 365 ma operating current i dd7a four bank interleaving reads (bl=4) with auto precharge with t rc =t rc (min); t ck =t ck (min); address and control inputs change only during active read or write commands. 5095 5050 5050 5050 ma
6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary i dd1 : operating current : one bank 1. typical case : v cc =2.5v, t=25c 2. worst case : v cc =2.7v, t=10c 3. only one bank is accessed with t rc (min), burst mode, address and control inputs on nop edge are changing once per clock cycle. i out = 0ma 4. timing patterns : ? ddr200 (100 mhz, cl=2) : t ck= 10ns, cl2, bl=4, t rcd= 2*t ck , t ras= 5*t ck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr266 (133mhz, cl=2.5) : t ck= 7.5ns, cl=2.5, bl=4, t rcd= 3*t ck , t rc= 9*t ck , t ras= 5*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr266 (133mhz, cl=2) : t ck =7.5ns, cl=2, bl=4, t rcd =3*t ck , t rc =9*t ck , t ras =5*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst ? ddr333 (166mhz, cl=2.5) : t ck =6ns, bl=4, t rcd =10*t ck , t ras =7*t ck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing; 50% of data changing at every burst i dd7a : operating current : four banks 1. typical case : v cc =2.5v, t=25c 2. worst case : v cc =2.7v, t=10c 3. four banks are being interleaved with t rc (min), burst mode, address and control inputs on nop edge are not changing. iout=0ma 4. timing patterns : ? ddr200 (100 mhz, cl=2) : t ck =10ns, cl2, bl=4, t rrd =2*t ck , t rcd =3*t ck , read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr266 (133mhz, cl=2.5) : t ck =7.5ns, cl=2.5, bl=4, t rrd =3*t ck , t rcd =3*t ck read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr266 (133mhz, cl=2) : t ck =7.5ns, cl2=2, bl=4, t rrd =2*t ck , t rcd =2*t ck read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst ? ddr333 (166mhz, cl=2.5) : t ck =6ns, bl=4, t rrd =3*t ck , t rcd =3*t ck , read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing; 100% of data changing at every burst detailed test conditions for ddr sdram i dd1 & i dd7a legend : a = activate, r = read, w = write, p = precharge, n = nop a (0-3) = activate bank 0-3 r (0-3) = read bank 0-3
7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary ddr sdram component electrical characteristics and recommended ac operating conditions ac characteristics 335 262 265/202 parameter symbol min max min max min max units notes access window of dqs from ck/ck# t ac -0.70 +0.70 -0.75 +0.75 -0.75 0.75 ns ck high-level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 ck low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 t ck 26 clock cycle time cl = 2.5 t ck (2.5) 6 13 7.5 13 7.5 13 ns 39, 44 cl = 2 t ck (2) 7.5 13 7.5 13 7.5/10 13 ns 39, 44 dq and dm input hold time relative to dqs t dh 0.45 0.5 0.5 ns 23, 27 dq and dm input setup time relative to dqs t ds 0.45 0.5 0.5 ns 23, 27 dq and dm input pulse width (for each input) t dipw 1.75 1.75 1.75 ns 27 access window of dqs from ck/ck# t dqsck -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 ns dqs input high pulse width t dqsh 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl 0.35 0.35 0.35 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.4 0.5 0.5 ns 22, 23 write command to ? rst dqs latching transition t dqss 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.20 0.20 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.20 0.20 0.2 t ck half clock period t hp t ch, t cl t ch, t cl t ch, t cl ns 30 data-out high-impedance window from ck/ck# t hz +0.70 +0.75 +0.75 ns 16, 36 data-out low-impedance window from ck/ck# t lz -0.70 -0.75 -0.75 ns 16, 36 address and control input hold time (fast slew rate) t ihf 0.75 0.90 0.90 ns 12 address and control input setup time (fast slew rate) t isf 0.75 0.90 0.90 ns 12 address and control input hold time (slow slew rate) t ihs 0.8 1 1 ns 12
8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary ddr sdram component electrical characteristics and recommended ac operating conditions (continued) ac characteristics 335 262 265/202 parameter symbol min max min max min max units notes address and control input setup time (slow slew rate) t iss 0.8 1 1 ns 12 address and control input pulse width (for each input) t ipw 2.2 2.2 2.2 ns load mode register command cycle time t mrd 12 15 15 ns dq-dqs hold, dqs to ? rst dq to go non-valid, per access t qh t hp - t qhs t hp - t qhs t hp - t qhs ns 22, 23 data hold skew factor t qhs 0.50 0.75 0.75 ns active to precharge command t ras 42 70,000 40 120,000 40 120,000 ns 30, 47 active to read with auto precharge command t rap 15 15 20 ns active to active/auto refresh command period t rc 60 60 65 ns auto refresh command period t rfc 72 75 78 ns 42 active to read or write delay t rcd 15 15 20 ns precharge command period t rp 15 15 20 ns dqs read preamble t rpre 0.9 1.1 0.9 1.1 0.9 1.1 t ck 37 dqs read postamble t rpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 37 active bank a to active bank b command t rrd 12 15 15 ns dqs write preamble t wpre 0.25 0.25 0.25 t ck dqs write preamble setup time t wpres 0 0 0 ns 18, 19 dqs write postamble t wpst 0.4 0.6 0.4 0.6 0.4 0.6 t ck 17 write recovery time t wr 15 15 15 ns internal write to read command delay t wtr 111t ck data valid output window na t qh - t dqsq t qh - t dqsq t qh - t dqsq ns 22 refresh to refresh command interval t refc 70.3 70.3 70.3 s 21 average periodic refresh interval t refi 7.8 7.8 7.8 s 21 terminating voltage delay to v cc t vtd 000ns exit self refresh to non-read command t xsnr 75 75 75 ns exit self refresh to read command t xsrd 200 200 200 t ck
9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary notes 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical ac and dc characteristics may be conducted at nominal reference/supply voltage levels, but the related speci? cations and device operation are guaranteed for the full voltage range speci? ed. 3. outputs measured with equivalent load: output o u t p u t (v ( v out o u t ) reference r e f e r e n c e point p o i n t 50? 5 0 ? v tt t t 30pf 3 0 p f 4. ac timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck/ck#), and parameter speci? cations are guaranteed for the speci? ed ac input levels under normal use conditions. the mini-mum slew rate for the input signals used to test the device is 1v/ns in the range between v il (ac) and v ih (ac). 5. the ac and dc input level speci? cations are as de? ned in the sstl_2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above [below] the dc input low [high] level). 6. v ref is expected to equal v ccq/2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise (non-common mode) on v ref may not exceed 2 percent of the dc value. thus, from v ccq/2 , v ref is allowed 25mv for dc error and an additional 25mv for ac noise. this measurement is to be taken at the nearest v ref bypass capacitor. 7. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 8. i dd is dependent on output loading and cycle rates. speci? ed values are obtained with mini-mum cycle time at cl = 2 for 262, and 263, cl = 2.5 for 335 and 265 with the outputs open. 9. enables on-chip refresh and address counters. 10. i dd speci? cations are tested after the device is properly initialized, and is averaged at the de? ned cycle rate. 11. this parameter is sampled. v cc = +2.5v 0.2v, v cc q = +2.5v 0.2v, v ref = vss, f = 100 mhz, t a = 25c, v out (dc) = v ccq/2 , v out (peak to peak) = 0.2v. dm input is grouped with i/o pins, re? ecting the fact that they are matched in loading. 12. for slew rates < 1 v/ns and to 0.5 vns. if the slew rate is < 0.5v/ns, timing must be derated: t is has an additional 50ps per each 100 mv/ns reduction in slew rate from 500mv/ns, while t ih is unaffected. if the slew rate exceeds 4.5 v/ns, functionality is uncertain. for 335, slew rates must be 0.5 v/ns. 13. the ck/ck# input reference level (for timing referenced to ck/ck#) is the point at which ck and ck# cross; the input reference level for signals other than ck/ck# is v ref . 14. inputs are not recognized as valid until v ref stabilizes. exception: during the period before v ref stabilizes, cke < 0.3 x v ccq is recognized as low. 15. the output timing reference level, as measured at the timing reference point indicated in note 3, is v tt . 16. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a speci? c voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). 17. the intent of the dont care state after completion of the postamble is the dqs- driven signal should either be high, low, or high-z and that any signal transition within the input switching region must follow valid input requirements. that is, if dqs transitions high (above v ih dc (min) then it must not transition low (below v ih dc) prior to t dqsh (min). 18. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. it is recommended that dqs be valid (high or low) on or before the write command. the case shown (dqs going from high-z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high during this time, depending on t dqss . 20. min (t rc or t rfc ) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd measurements is the largest multiple of t ck that meets the maximum absolute value for t ras . 21. the refresh period 64ms. this equates to an aver-age refresh rate of 7.8125s. however, an auto refresh command must be asserted at least once every 70.3s; burst refreshing or posting by the dram controller greater than eight refresh cycles is not allowed. 22. the valid data window is derived by achieving other speci? cations: t hp (t ck /2), t dqsq , and t qh (t qh = t hp - t qhs ). the data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55, beyon which functionality is uncertain. figure 7, derating data valid window, shows derating curves for duty cycles ranging between 50/50 and 45/55. 23. each byte lane has a corresponding dqs. 24. this limit is actually a nominal value and does not result in a fail value. cke is high during refresh command period (t rfc [min]) else cke is low (i.e., during standby). 25. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through to the target ac level, v il (ac) or v ih (ac).reach at least the target ac level. b. after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc). 26. jedec speci? es ck and ck# input slew rate must be 1v/ns (2v/ns differentially). 27. dq and dm input slew rates must not deviate from dqs by more than 10 percent. if the dq/ dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rate exceeds 4v/ns, functionality is uncertain. for 335, slew rates must be 0.5 v/ns. 28. v cc must not vary more than 4 percent if cke is not active while any bank is active. 29. the clock is allowed up to 150ps of jitter. each timing parameter is allowed to vary by the same amount. t hp min is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs, collectively during bank active. 30. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satis? ed prior to the internal precharge command being issued. 31. any positive glitch must be less than 1/3 of the clock and not more than +400mv or 2.9v, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mv or 2.2v, whichever is more positive.
10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary 32. normal output drive curves: a. the full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure 8, pull-down characteristics. b. the variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 8, pull-down characteristics. c. the full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the v-i curve of figure 9, pull-up characteristics. d. the variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the v-i curve of figure 9, pull-up characteristics. e. the full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1v to 1.0v, and at the same voltage and temperature. f. the full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source volt-ages from 0.1v to 1.0v. 33. the voltage levels used are derived from a mini-mum v cc level and the referenced test load. in practice, the voltage levels obtained from a properly terminated bus will provide signi? cantly different voltage values. 34. v ih overshoot: v ih (max) = v cc q + 1.5v for a pulse width !5 3ns and the pulse width can not be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = -1.5v for a pulse width !5 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 35. v cc and v cc q must track each other. 36. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. t lz (min) will prevail over t dqsck (min) + t rpre (max) condition. 37. t rpst end point and t rpre begin point are not referenced to a speci? c voltage level but specify when the device output is no longer driving (t rpst ), or begins driving (t rpre ). 38. during initialization, v ccq , v tt , and v ref must be equal to or less than v cc + 0.3v. alternatively, v tt may be 1.35v maximum during power up, even if v cc /v ccq are 0.0v, provided a minimum of 42 0 of series resistance is used between the v tt supply and the input pin. 39. the current part operates below the slowest jedec operating frequency of 83 mhz. as such, future die may not re? ect this option. 40. random addressing changing and 50 percent of data changing at every transfer. 41. random addressing changing and 100 percent of data changing at every transfer. 42. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refresh command is registered, cke must be active at each rising clock edge, until tref later. 43. i dd 2n speci? es the dq, dqs, and dm to be driven to a valid high or low logic level. i dd 2q is similar to i dd 2f except i dd 2q speci? es the address and control inputs to remain stable. although i dd 2f, i dd 2n, and i dd 2q are similar, i dd 2f is worst case. 44. whenever the operating frequency is altered, not including jitter, the dll is required to be reset. this is followed by 200 clock cycles. 45. leakage number re? ects the worst case leakage possible through the module pin, not what each memory device contributes. 46. when an input signal is high or low, it is de? ned as a steady state logic high or low. 47. the 335 speed grade will operate with t ras (min) = 40ns and t ras (max) = 120,000ns at any slower frequency.
11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary package dimensions for bd4 * all dimensions are in milimeters and (inches) 67.56 (2.666) max 0.99 0.10 (0.039 0.004) 6.35 (0.250) max. 2.31 (0.091) ref. 4.19 (0.165) 1.80 (0.071) 3.99 (0.157) min. 47.40 (1.866) 11.40 (0.449) 31.75 (1.25) 3.98 0.1 (0.157 0.004) 20 (0.787) ordering information for bd4 part number speed cas latency t rcd t rp height* w3eg72128s335bd4-xg 166mhz/333mb/s 2.5 3 3 31.75 (1.25") w3eg72128s262bd4-xg 133mhz/266mb/s 2 2 2 31.75 (1.25") w3eg72128s265bd4-xg 133mhz/266mb/s 2.5 3 3 31.75 (1.25") w3eg72128s202bd4-xg 100mhz/200mb/s 2 2 2 31.75 (1.25") notes: ? consult factory for availability of rohs compliant products. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lo wer case -x in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consul t factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
12 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary package dimensions for ad4 * all dimensions are in milimeters and (inches) 35.05 (1.138) max. 2.31 (0.091) ref. 2.0 (0.079) 67.56 (2.666) max. 4.19 (0.165) 1.80 (0.071) 20 (0.787) 47.40 (1.866) 11.40 (0.449) p1 3.98 0.1 (0.157 0.004) 0.99 0.10 (0.039 0.004) 6.35 (0.250) max. 3.99 (0.157) min. ordering information for ad4 part number speed cas latency t rcd t rp height* w3eg72128s335ad4-xg 166mhz/333mb/s 2.5 3 3 35.05 (1.138") w3eg72128s262ad4-xg 133mhz/266mb/s 2 2 2 35.05 (1.138") w3eg72128s265ad4-xg 133mhz/266mb/s 2.5 3 3 35.05 (1.138") w3eg72128s202ad4-xg 100mhz/200mb/s 2 2 2 35.05 (1.138") notes: ? consult factory for availability of rohs compliant products. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lo wer case -x in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consul t factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
13 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary part numbering guide w 3 e g 72 128 s xxx d4 x -x g wedc memory ddr gold bus width depth 2.5v speed (mhz) package 200 pin i = industrial component vendor name (m = micron) (s = samsung) g = rohs compliant
14 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs w3eg72128s-ad4 -bd4 august 2005 rev. 3 preliminary document title 1gb C 2x64mx72 ddr sdram unbuffered ecc w/pll revision history rev # history release date status rev 0 created 7-23-03 advanced rev 1 added ad4 and bd4 package height option 4-6-04 preliminary rev 2 added ac specs 10-4-04 preliminary rev 3 3.1 added part number matrix 8-05 preliminary

▲Up To Search▲

Price & Availability of W3EG72128SXXXD4ISG

	To Download W3EG72128SXXXD4ISG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .